1. Field of the Invention
This invention relates particularly to a buffer circuit and a bias circuit both of which electrically process signals such as small amplitude signals (each corresponding to a signal in which the difference between a voltage level indicative of a high logical level and a voltage level indicative of a low logical level is small, such as a signal whose amplitude is of 200 mV with a substantially central level between a ground potential and 2 V as the center when a source potential level is of 2 V).
2. Description of the Related Art
This type of buffer circuit includes a transistor provided on the signal input side and a transistor provided on the signal output side. In the buffer circuit, a small amplitude signal having a voltage level in the vicinity of a threshold voltage of a transistor thereof is inputted to the signal input side transistor. Further, a small amplitude signal having a voltage level in the vicinity of a threshold voltage of a transistor provided within an external circuit for receiving the output of the buffer circuit therein is outputted from the signal output side transistor.
The buffer circuit, which electrically handles the small amplitude signals referred to above, can transfer signals at high speed as compared with a buffer circuit composed of transistors whose switching operations are performed in the saturation region. Thus, the buffer circuit is used particularly in an electronic circuit that needs a high-speed operation.
In a semiconductor manufacturing step, however, there may be cases where a threshold voltage of each of the transistors deviates, slightly from a design value due to variations of manufacture which take place while manufacturing the transistors. The deviation of the threshold voltage of each transistor from the design value is a significant factor which exerts a bad influence on the operation of the buffer circuit. Thus, a buffer circuit has been desired which is insensitive to the deviation from the threshold voltage of the transistor.